Developments in the field of integrated circuits have lead to increasingly complex integrated circuit memories. Memory chips which are capable of storing millions of bits of digital information require increasingly small feature sizes. These very small sized electrical components have become increasingly taxed by requirements which test the limits of successful operation. A feature of importance to the current invention is the electrical supply line which delivers current to the various memory cells contained in a random access memory chip, particularly dynamic random access memory chips.
Each memory cell in an dynamic random access memory (DRAM) circuit utilizes a storage capacitor which is charged to a relatively low or high voltage to indicate either of two corresponding binary states. Because of leakage within the cell, the charge existing on the memory cell storage capacitor must be periodically refreshed to maintain the correct charge and associated binary state. The memory cell storage capacitor is refreshed to its high or low voltage condition either during the process of being read, or after a specific time interval in a refresh operation.
Refresh is performed by activating the particular memory cell in question. The cell is activated by appropriately indicating the cell from the numerous cells available on a memory array. In the case of a folded bit line type DRAM, this is done by effectuating a high condition on a word line and enabling the folded bit line which is connected to the cell. When the memory cell is activated, the storage capacitor is electrically connected to the bit line. If the charge on the storage capacitor is high, then the voltage of the connected bit line is increased when the capacitor discharges positive current onto the bit line. If the charge on the storage capacitor is low, then the voltage of the bit line is decreased when the capacitor takes positive current from the bit line.
Prior to connecting the memory cell storage capacitor to the bit line, the bit line is set to an intermediate voltage which allows the high or low charge in the memory cell to increase or decrease the voltage on the bit line. This intermediate voltage is advantageously achieved in the folded bit line configuration using two complementary bit lines which are oppositely charged when the cell is being written into or refreshed. This arrangement allows the complementary charges stored on the two complementary bit lines to equilibrate to an intermediate voltage by connecting them together and to an equilibrating voltage reference prior to the connection of the memory cell capacitor to its associated bit line.
The connection of the memory cell storage capacitor to the equilibrated bit line causes the voltage on the bit line to change either upwardly or downwardly in response to the relatively high or low state of the storage capacitor prior to connection with the bit line. The complementary bit line pair is connected to a positive electrical supply using a pull-up circuit which increases the voltage of the relatively more positive of the bit lines in the pair. Conversely, the bit line pair is also connected to ground or other relatively more negative electrical supply using a pull-down circuit which decreases the voltage of the other bit line. The pull-up circuit is advantageously in the form of a sense amplifier, such as a p-channel sense amplifier. The pull-down circuit is also advantageously in the form of a sense amplifier, such as an n-channel sense amplifier. The voltage produced on the bit line by the appropriate sense amplifier thus provides a refresh charge to the memory cell storage capacitor at the correct voltage level.
The pull-up circuit draws positive current from a relatively positive electrical supply line during the pull-up period while the storage capacitor is charging to its correct voltage. As the storage capacitor is charging to the high voltage, the pull-up circuit may demand a significant amount of current from the electrical supply line. In some cases the current demanded is sufficient to cause a voltage decrease transient on the supply line. This is a potential problem which may be exacerbated by numerous individual memory cells being simultaneously activated. While simultaneous access reduces the number of refresh cycles necessary in a given time, it also places increased current demands upon the supply line and, in practice, causes undesirable decreased voltage transients.
Prior DRAM circuits of this type have attempted to decrease this problem of voltage decrease transients by using a capacitor in conjunction with the pull-up circuit sense amplifier. This approach has not been sufficiently effective to eliminate the transient problem. Increasing the capacitance causes substantial decreases in speed which can not be accepted. Accordingly, there remains a need for more effective circuitry and methods for supplying power to pull-up circuits for folded bit line DRAM's and other random access memory chips having similar power transient problems.